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TC90A66F
Preliminary TOSHIBA CMOS Digital Integrated Circuit
Silicon Monolithic
TC90A66F
PAP/PIP/POP Controller for Wide-Screen TVs (PAL/NTSC)
With built-in AD and DA converters (ADC/DAC), the TC90A66F is a picture-and-picture (PAP)/picture-in-picture (PIP)/picture-out-picture (POP) controller IC for PAL and NTSC formats. It is used in combination with field memory, video signal processor ICs. The TC90A66F enables a variety of picture display functions. The IC is optimal to provide wide-screen TVs with additional functionality.
Features
* * * Two-channel 8-bit ADC, three-channel 8-bit DAC, clamp circuit, and multiplexer integrated on single chip External field memory Recommended memory: MSM51V8221, MSM51V8222 (By Oki) Picture display functions PAP display PIP display POP display Half-picture left and right sides of 16:9 screen (Motion Picture mode or Still mode selectable) 4:3 or 16:9 aspect ratio (Motion Picture mode or Still mode selectable) 4:3 aspect ratio (3 pictures in Still mode, 1 picture in Motion Picture mode and 2 pictures in Still mode, or Strobe mode selectable) Multi-picture still Channel search * * * * * Display of up to 24 still pictures per screen 9, 12, or 16 picture search (Still mode, Strobe mode, or 1 picture in Motion Picture mode selectable) Variable frame width and frame color Built-in horizontal and vertical filters 3.3-V single power supply Package: QFP144 Weight: 4.64 g (typ.)
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2001-06-07
www..com
I2C bus for micro controller interface
TC90A66F
Pin Assignment
TIMRST PWRST HYOJUN KAYS YS RVD RHD VDD RCK RHREF VSS RMCKI RMCK ERRST EREN RRST REN RDAY7 RDAY6 RDAY5 RDAY4 RDAY3 RDAY2 RDAY1 RDAY0 VDD RDAC7 RDAC6 RDAC5 RDAC4 RDAC3 RDAC2 RDAC1 RDAC0 WDAY0 WDAY1
108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73
TESO IICNR SADSEL SACN VSS SCL SDA TEST4 TEST3 TEST2 TEST1 TEST0 VDD T107 T106 T105 T104 T103 T102 T101 T100 CNT6 CNT5 CNT4 CNT3 VSS DAVDD YOUT DAVSS IOUT DAVDD QOUT VB2 VB1 VREF ADBIAS
109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144
TC90A66F
72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37
WDAY2 WDAY3 WDAY4 WDAY5 WDAY6 WDAY7 VSS WDAC0 WDAC1 WDAC2 WDAC3 WDAC4 WDAC5 WDAC6 WDAC7 WRST WEN WIEN EWRST EWEN EWIEN VSS WMCK VSS EWMCK VDD WHREFS WCKS VSS WHDS WVDS MOH HRST VDD WHREFE WCKE
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 ADVDD YINS ADVSS IINS ADVDD QINS ADVSS VRTY VRBY VRTC VRBC ADVDD YINE ADVSS IINE AVDD QINE AVSS VDD CNT2 CNT1 CNT0 CLAMP TIN9 TIN8 TIN7 TIN6 TIN5 TIN4 TIN3 TIN2 TIN1 TIN0 WVDE WHDE VSS
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TC90A66F
System Block Diagram
Output signal Y I Q SCL SDA -COM YOUT IOUT QOUT SDA SCL SUB VCD1 TA1270AF YIN CIN Sub picture (S) Image input signal YIN CIN Y1IN I1IN Q1IN YS Y2IN I2IN Q2IN YOUT IOUT QOUT HD VD WVDS WHDS RVD RHD SDA SCL SUB VCD2 TA1270AF YIN CIN Sub picture (E) Image input signal YIN CIN YOUT IOUT QOUT YINE IINE QINE PAP/PIP/POP TC90A66F YINS IINS QINS YOUT IOUT QOUT YS SDA SCL
PLL circuit RCK RHREF
RDAY RDAC RMCK WDAY WDAC WMCK
2M MEMORY*2 MSM51V8221
HD
VD
WVDE WHDE
WCKS WHREFS WCKE WHREFE PLL circuit PLL circuit
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TC90A66F
TC90A66F Block Diagram
(not required in 2M mode) MAIN -COM IN SDA SCL A YIN IIN QIN YIN IIN QIN (S) (S) (S) (E) (E) (E) C L M P C L M P WDAY 7 to 0 M P X M P X A/D Horizontal filter A/D Line memory Vertical filter Y/IQ separator WMCK WRST RMCK RDAY WDAC 1200 fh WENY 1200 fh 7 to 0 7 to 0 (4M/2M) WENC (4M/2M) WIE RRST REN RMCKI RDAC 7 to 0 IIC BUS 2M memory (MSM51V8221) OUT IN 2M memory (MSM51V8221) OUT
Vertical filter Odd/Even detector circuit Sub picture S WVDS WHDS WCKS WHREF Sub picture E WVDE WHDE WCKE WHREFE Main picture RVD RHD RCK RHREF Line memory Generates system clock for write 2400 fh (4M/2M) A Generates system clock for write 2400 fh (4M/2M) Generates control signal for write
D/A Output processor (frame color select, Y/C phase adjustment) Code processor D/A D/A
YOUT IOUT QOUT VREF
Stand processor
VB1 VB2 Picture display switch signal YS
Control signals for write
PWRST Generates system clock for read 2400 fh (4M/2M) Generates control signal for read Control signals for read Memory use switch signal
MOH
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TC90A66F
Pin Functions (144-pin QFP)
Pin Pin Name Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 ADVDD YINS ADVSS IINS ADVDD QINS ADVSS VRTY VRBY VRTC VRBC ADVDD YINE ADVSS IINE AVDD QINE AVSS VDD CNT2 CNT1 CNT0 CLAMP TIN9 TIN8 TIN7 TIN6 TIN5 TIN4 TIN3 TIN2 TIN1 TIN0 WVDE WHDE VSS WCKE WHREFE VDD HRST MOH I/O I I I I I I I I I I O O O O I I I I I I I I I I I I I Power supply for A/D (3.3 V) A/D Y signal (S system) input GND for A/D A/D I signal or R-Y signal (S system) input Power supply for A/D (3.3 V) A/D Q signal or B-Y signal (S system) input GND for A/D Reference voltage for A/D Y signal (top) Reference voltage for A/D Y signal (bottom) Reference voltage for A/D I, Q signal (top) Reference voltage for A/D I, Q signal (bottom) Power supply for A/D (3.3 V) A/D Y signal (E system) input GND for A/D A/D I signal or R-Y signal (E system) input Power supply for analog circuit (3.3 V) A/D Q signal or B-Y signal (E system) input GND for analog circuit Power supply (3.3 V) Test output pin Test output pin Test output pin Clamp signal monitor output Test input pin (connect to GND) Test input pin (connect to GND) Test input pin (connect to GND) Test input pin (connect to GND) Test input pin (connect to GND) Test input pin (connect to GND) Test input pin (connect to GND) Test input pin (connect to GND) Test input pin (connect to GND) Test input pin (connect to GND) (E system) vertical sync signal input (It can be inverted using I2C bus) (E system) horizontal sync signal input (It can be inverted using I C bus) GND (E system) system clock input (Note1)
2
Function
(Note1) (Note1)
I/O (E system) PLL phase comparison output O O Power supply (3.3 V) Unit adjusting pin Memory use switch signal [(YCS (L) TC90A66F (H))
Note1: Supports 5 V interface.
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TC90A66F
Pin Pin Name Number 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 WVDS WHDS VSS WCKS WHREFS VDD EWMCK VSS WMCK VSS EWIEN EWEN EWRST WIEN WEN WRST WDAC7 WDAC6 WDAC5 WDAC4 WDAC3 WDAC2 WDAC1 WDAC0 VSS WDAY7 WDAY6 WDAY5 WDAY4 WDAY3 WDAY2 WDAY1 WDAY0 RDAC0 RDAC1 RDAC2 RDAC3 RDAC4 RDAC5 RDAC6 RDAC7 VDD RDAY0 I/O I I I O O O O O O O O O O O O O O O O O O O O O O O O O I I I I I I I I I Function (S system) vertical sync signal input (It can be inverted using I2C bus) (S system) horizontal sync signal input (It can be inverted using I C bus) GND (S system) system clock input (S system) PLL phase comparison output Power supply (3.3 V) (E system) write clock output for field memory GND (S system) write clock output for field memory GND (E system) field memory input enable (E system) field memory write enable (E system) field memory write reset (S system) field memory input enable (S system) field memory write enable (S system) field memory write reset IQ or sub picture (E system) signal output (field memory write signal/MSB) IQ or sub picture (E system) signal output (field memory write signal/ IQ or sub picture (E system) signal output (field memory write signal/ IQ or sub picture (E system) signal output (field memory write signal/ IQ or sub picture (E system) signal output (field memory write signal/ IQ or sub picture (E system) signal output (field memory write signal/ IQ or sub picture (E system) signal output (field memory write signal/ :) :) :) :) :) :) (Note1)
2
(Note1) (Note1)
IQ or sub picture (E system) signal output (field memory write signal/LSB) GND Y or sub picture (S system) signal output (field memory write signal/MSB) Y or sub picture (S system) signal output (field memory write signal/ Y or sub picture (S system) signal output (field memory write signal/ Y or sub picture (S system) signal output (field memory write signal/ Y or sub picture (S system) signal output (field memory write signal/ Y or sub picture (S system) signal output (field memory write signal/ Y or sub picture (S system) signal output (field memory write signal/ :) :) :) :) :) :)
Y or sub picture (S system) signal output (field memory write signal/LSB) IQ or sub picture (E system) signal input (field memory read signal/LSB) IQ or sub picture (E system) signal input (field memory read signal/ : ) IQ or sub picture (E system) signal input (field memory read signal/ : ) IQ or sub picture (E system) signal input (field memory read signal/ : ) IQ or sub picture (E system) signal input (field memory read signal/ : ) IQ or sub picture (E system) signal input (field memory read signal/ : ) IQ or sub picture (E system) signal input (field memory read signal/ : ) IQ or sub picture (E system) signal input (field memory read signal/MSB) Power supply (3.3 V) Y or sub picture (S system) signal input (field memory read signal/LSB) (Note1) (Note1) (Note1) (Note1) (Note1) (Note1) (Note1) (Note1) (Note1)
Note1: Supports 5 V interface.
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TC90A66F
Pin Pin Name Number 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 RDAY1 RDAY2 RDAY3 RDAY4 RDAY5 RDAY6 RDAY7 REN RRST EREN ERRST RMCK RMCKI VSS RHREF RCK VDD RHD RVD YS KAYS HYOJUN PWRST TIMRST TESO IICNR SADSEL SACN VSS SCL SDA TEST4 TEST3 TEST2 TEST1 TEST0 VDD TIO7 TIO6 TIO5 TIO4 TIO3 TIO2 I/O I I I I I I I O O O O O I O I I I O O O I I O I I O I Function Y or sub picture (S system) signal input (field memory read signal/ :) Y or sub picture (S system) signal input (field memory read signal/ : ) Y or sub picture (S system) signal input (field memory read signal/ : ) Y or sub picture (S system) signal input (field memory read signal/ : ) Y or sub picture (S system) signal input (field memory read signal/ : ) Y or sub picture (S system) signal input (field memory read signal/ : ) Y or sub picture (S system) signal input (field memory read signal/MSB) (S system) field memory read enable (S system) field memory read reset (E system) field memory read enable (E system) field memory read reset (S/E system) read clock output for field memory RMCK input (phase adjustment) GND PLL phase comparison output for main picture System clock input for main picture Power supply (3.3 V) Horizontal sync single input for main picture (It can be inverted using I2C bus) Vertical sync single input for main picture (It can be inverted using I C bus) YS signal output Wallpaper YS signal output Standard/non-standard signal output [standard (L)/non-standard (H)] System reset input [reset (L)] Test reset input [reset (H)/normal (L)] Test monitor output I2C bus noise reduction circuit [on (H)/off (L)] Main/sub sub address switch [main (H)/sub (L)] I2C bus acknowledge output pin GND I2C bus serial clock input
2 2
(Note1) (Note1) (Note1) (Note1) (Note1) (Note1) (Note1)
(Note1)
(Note1) (Note1)
(Note1) (Note1)
I/O I C bus serial data input (IN)/acknowledge (OUT) I I I I I Test input pin (connect to GND) Test input pin (connect to GND) Test input pin (connect to GND) Test input pin (connect to GND) Test input pin (connect to GND) Power supply (3.3 V)
I/O Test input/output pin (normally, open) I/O Test input/output pin (normally, open) I/O Test input/output pin (normally, open) I/O Test input/output pin (normally, open) I/O Test input/output pin (normally, open) I/O Test input/output pin (normally, open)
Note1: Supports 5 V interface.
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TC90A66F
Pin Pin Name Number 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 TIO1 TIO0 CNT6 CNT5 CNT4 CNT3 VSS DAVDD YOUT DAVSS IOUT DAVDD QOUT VB2 VB1 VREF ADBIAS I/O I/O Test input/output pin (normally, open) I/O Test input/output pin (normally, open) O O O O O O O I Test output pin Test output pin Test output pin Test output pin GND Power supply for D/A (3.3 V) Y Signal output D/A GND I signal or R-Y signal output Power supply for D/A (3.3 V) Q signal or B-Y signal output D/A bias D/A bias D/A reference bias (supply 2.3 V) A/D bias Function
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2001-06-07
TC90A66F
Pin Description
Pin Number 2 Pin Name YINS Y-signal (S system) analog input Input amplitude is 1 Vp-p typical. 4 IINS I or R-Y signal (S system) analog input Input amplitude is 1 Vp-p typical. 6 QINS Q or B-Y signal (S system) analog input Input amplitude is 1 Vp-p typical. 8 VRTY High-level reference power supply pin for ADC Y signal. Sets the upper limit of the ADC dynamic range. Fixed to 2.2 V (typ.) by internal resistance type potential division. Connect 0.1 F bypass capacitor between the pin and GND. Low-level reference power supply voltage for ADC Y signal. Sets the lower limit of the ADC dynamic range. Fixed to 1.1 V (typ.) by internal resistance type potential division. Connect 0.1 F bypass capacitor between the pin and GND. High-level reference power supply pin for ADC IQ signal. Sets the upper limit of the ADC dynamic range. Fixed to 2.2 V (typ.) by internal resistance type potential division. Connect 0.1 F bypass capacitor between the pin and GND. Low-level reference power supply voltage for ADC IQ signal. Sets the lower limit of the ADC dynamic range. Fixed to 1.1 V (typ.) by internal resistance type potential division. Connect 0.1 F bypass capacitor between the pin and GND. Y signal (E system) analog input Input amplitude is 1 Vp-p typical. 15 IINE I or R-Y signal (E system) analog input Input amplitude is 1 Vp-p typical. 17 QINE Q or B-Y signal (E system) analog input Input amplitude is 1 Vp-p typical. 23 CLAMP Clamp signal monitor output pin. Can monitor clamp pulse start/stop position set at 24h or 25h. Outputs signal for the last data (S or E system) transfer. 34 WVDE (E system) vertical sync signal input pin. (It can be inverted using I2C bus) Inputs vertical sync signal from VCD for sub picture E. It is composing 5 V interface. For negative polarity input, set sub address [26H: EVINV] to L (negative polarity input). (E system) horizontal sync signal input pin. (It can be inverted using I2C bus) Inputs horizontal sync signal from VCD for sub picture E. It is composing 5 V interface. For negative polarity input, set sub address [26H: EHINV] to L (negative polarity input). (E system) write clock input pin. Inputs from the external PLL circuit. It is composing 5 V interface. Inputs 2400 fH for both 4M and 2M memory mode. 38 WHREFE (E system) PLL phase comparison output. The HREF signal obtained by the I/N divider circuit or the phase comparison result of sub picture (E) horizontal sync signal. 40 41 HRST MOH Unit adjustment (WS/WE/R switch able) External field memory use signal output pin. Output amplitude is 3.3 Vp-p typical. Setting sub address [21H: MOH] to H uses TC90A66F; setting to L sets all memory output pins to Hi-Z. 42 WVDS (S system) vertical sync signal input pin. (It can be inverted using I2C bus) Inputs vertical sync signal from VCD for sub picture S. It is composing 5 V interface. For negative polarity input, set sub address [27H: WVINV] to L (negative polarity input). (S system) horizontal sync signal input pin. (It can be inverted using I2C bus) Inputs horizontal sync signal from VCD for sub picture S. It is composing 5 V interface. For negative polarity input, set sub address [27H: WHINV] to L (negative polarity input). (S system) write clock input pin. Inputs from the external PLL circuit. It is composing 5 V interface. Inputs 2400 fH for both 4M and 2M memory mode. Function
9
VRBY
10
VRTC
11
VRBC
13
YINE
35
WHDE
37
WCKE
43
WHDS
45
WCKS
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TC90A66F
Pin Number 46 Pin Name WHREFS (S system) PLL phase comparison output. The HREF signal obtained by the I/N divider circuit or the phase comparison result of sub picture (S) horizontal sync signal. This signal is used to control the external VCO voltage. 48 EWMCK Outputs sub picture E write clock to external field memory. Output amplitude is 3.3 Vp-p typical. 50 WMCK Outputs sub picture S write clock to external field memory. Output amplitude is 3.3 Vp-p typical. 52 EWIEN Control signal output pin for external field memory (sub picture E). Output amplitude is 3.3 Vp-p typical. 53 EWEN Control signal output pin for external field memory (sub picture E). Output amplitude is 3.3 Vp-p typical. 54 EWRST Control signal output pin for external field memory (sub picture E). Output amplitude is 3.3 Vp-p typical. 55 WIEN Control signal output pin for external field memory (sub picture S). Output amplitude is 3.3 Vp-p typical. 56 WEN Control signal output pin for external field memory (sub picture S). Output amplitude is 3.3 Vp-p typical. 57 WRST Control signal output pin for external field memory (sub picture S). Output amplitude is 3.3 Vp-p typical. 58 to 65 WDAC7-0 Output signal to write to external field memory. (I, Q or E system). Output amplitude is 3.3 Vp-p typical. Connect only when using 4M memory. MSB: WDAC7, LSB: WDAC0 67 to 75 WDAY7-0 Output signal to write to external field memory. (Y or S system). Output amplitude is 3.3 Vp-p typical. MSB: WDAY7, LSB: WDAY0 75 to 82 RDAC0-7 Input signal to read from external field memory (I, Q or E system). It is composing 5 V interface. Connect only when using 4M memory. MSB: RDAC7, LSB: RDAC0 84 to 91 RDAY0-7 Input signal to read from external field memory (Y or S system). It is composing 5 V interface. MSB: RDAY7, LSB: RDAY0 92 REN Control signal output pin for external field memory (sub picture S). Output amplitude is 3.3 Vp-p typical. 93 RRST Control signal output pin for external field memory (sub picture S). Output amplitude is 3.3 Vp-p typical. 94 EREN Control signal output pin for external field memory (sub picture E). Output amplitude is 3.3 Vp-p typical. 95 ERRST Control signal output pin for external field memory (sub picture E). Output amplitude is 3.3 Vp-p typical. 96 RMCK Outputs read clock to external field memory. Output amplitude is 3.3 Vp-p typical. Outputs 1200 fH for both 4M and 2M memory. 97 RMCKI RMCK phase adjustment input pin. Inputs RMCK. Function
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TC90A66F
Pin Number 99 Pin Name RHREF Function PLL phase compare output pin for main picture. The HREF signal obtained by the I/N divider circuit or the phase comparison result of RHD signal. This signal is used to control the external VCO voltage. 100 RCK Read clock input pin. It is composing 5 V interface. Inputs from the external PLL circuit. Inputs 2400 fH for both 4M and 2M memory. 102 RHD Horizontal sync signal input pin for main picture (read). Inputs horizontal sync signal from VCD for main picture. It is composing 5 V interface (negative polarity input). For negative polarity input, set sub address [28H: RHINV] to non-inversion (L). Vertical sync signal input pin for main picture (read). Inputs vertical sync signal from VCD for main picture. It is composing 5 V interface (negative polarity input). For negative polarity input, set sub address [28H: RVINV] to non-inversion (L). Main/sub picture switch timing signal output pin. Output amplitude is 3.3 Vp-p typical. When the YS signal is High, displays sub picture. Wallpaper YS signal output. Standard/non-standard signal output pin [standard (L)/non-standard (H)] System reset input pin. When low input, it carries out the reset. At least 1 V is required as reset duration. 110 IICNR I2C bus noise reduction circuit setting pin. When set to on (connect to VDD), data are latched once by the internal clock, then written to register. When set to off (connect to GND), data are written to register directly. Sub address of main/sub picture switching pin. [main (H)/sub (L)] Normally, set to L (enables sub addresses 00h to 7Fh). 112 114 115 SACN SCL SDA I2C bus acknowledge output pin. I2C bus serial clock input pin. It is composing 5 V interface. I2C bus serial data input/acknowledge output pin. It is composing 5 V interface. Y signal output pin. Output amplitude is 0.9 Vp-p typical. I signal output pin. Output amplitude is 0.9 Vp-p typical. Q signal output pin. Output amplitude is 0.9 Vp-p typical. Bias pin for DAC. Connect a 0.1 F bypass capacitor between the pins and GND. 143 VREF DAC reference voltage input pin. Reference voltage is 2.3 V typical. 144 ADBIAS Bias pin for ADC. Connect a 0.1 F bypass capacitor between the pin and AGND.
103
RVD
104 105 106 107
YS KAYS HYOJUN PWRST
111
SADSEL
136 138 140 141 to 142
YOUT IOUT QOUT VB2-1
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TC90A66F
Example of Typical A/D Converter Input Level for Luminance Signal
Dec. 2.2 V 100 (IRE) 255 228 HEX FFH E4H
1.1 V
0.71 V pedestal clamp value
0 (IRE) 0.27 V 1.1 V -40 (IRE) signal amplitude: 1.0 Vp-p (100% white)
63 0
3FH 00H
Example of Typical A/D Converter Input Level for Chrominance Signal
Dec. 2.2 V 255 251 HEX FFH EBH
0.5 V 1.1 V
136
88H
0.5 V
reference potential clamp value 21 0 15H 00H
1.1 V signal amplitude: 1.0 Vp-p
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TC90A66F
Example of Typical D/A Converter Output Level for Luminance Signal
Dec. 3.3 V 100 (IRE) 255 228 HEX FFH E4H
1.0 V
0.64 V
0 (IRE) 0.25 V 2.3 V -40 (IRE) signal amplitude: 0.9 Vp-p (100% white)
63 0
3FH 00H
Example of Typical D/A Converter Output Level for Chrominance Signal
Dec. 3.3 V 3.25 V 255 243 HEX FFH E3H
0.45 V 1.1 V
2.8 V
128
80H
0.45 V
2.35 V 2.3 V signal amplitude: 0.9 Vp-p
13 0
0DH 00H
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TC90A66F
Picture Display Function
Sub picture (S)
Main picture (E)
Sub picture (S)
2-picture (PAP) display 4:3 aspect ratio (full picture can be displayed) sub picture (S), (E): motion or still (pictures can be exchanged)
1-picture display (full picture can be used)
Sub picture (S)
Multi search pictures Sub picture (S): motion or still Sub picture (E): 9 or 12 still pictures, strobe display or only 1 motion picture and others still.
Main picture
sub picture (S) sub picture (S) sub picture (S)
Main picture sub picture (S) PIP display Sub picture: 16:9 or 4:3 aspect ratio Motion or still Main picture: display using TC90A18AF (EDWAC)
3-picture POP display Sub picture: 4:3 aspect ratio Still, strobe, only 1 motion picture Main picture: display using TC90A18AF (EDWAC)
Multiple picture search using the whole screen 12 or 9 still pictures, strobe display, only 1 motion picture and others still
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TC90A66F
I C Bus Address Setting Table
Sub Address Dec 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 FRFI ROEFON ROEALT RGAME RFISW DWSW RFALT RRH11 10 RHSIZ11 10
RHYSCE11 RHYSCS11 RHYSBE11 RHYSBS11 RHYSAE11 RHYSAS11
2
MSB 15 MYPH2 14 1 13 0 YSBACT MBLKIQ7 MMWIQ7 6 6 5 5 12 11 10 RCKINV YSBCLR 2 2 9 RREPH1 YSACLR 1 1 0 0 MBLKY7 MMWY7 6 6 5 5 4 4 3 3 2 2 1 1 8 0 7 M4M2 6 SESW 5 4 3 2 1
LSB 0
MYQPH0 RRSTINV FRACLR 4 4 YSCCLR 3 3
0 0
10 10
9 9
RVYSAE9 RVYSAS9
8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8
7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7
6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6
5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5
4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4
3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
10 10
9 9
RVYSBE9 RVYSBS9
10 10
9 9
RVYSCE9 RVYSCS9
9 RVSIZ9 9 RRV9
Note2: Set 0 in blank columns.
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Sub Address Dec 19 1A 1B 1C 1D 1E 1F 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 30 31 32 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 SCLPST7 ECLPST7 WPLHS WHIHYO RHIHYO
JVLOCHG
MSB 15 14 13 12 11 10 9 RWRN9 RWRA9 RHRFTH RHRFIV RHINV2 RCKCHG PRHP11
RPLLPH11
LSB 8 8 8 8 8 8 8 8 8 8 8 8 0 0 7 7 7 7 7 7 7 7 7 7 7 7
SCLPED7 ECLPED7
6 6 6 6 6 6 6 6 6 6 6 6 6 6 HDWDT7 6 6 6 6 6 6 6 6 6 6 6 6
5 5 5 5 5 5 5 5 5 5 5 5 5 5 6 5 5 5 5 5 5 5 5 5 5 5 5
4 4 4 4 4 4 4 4 4 4 4 4 4 4 5 4 4 4 4 4 4 4 4 4 4 4 4
3 3 3 3 3 3 3 3 3 3 3 3 3 3 4 3 3 3 3 3 3 3 3 3 3 3 3
2 2 2 2 2 2 2 2 2 2 2 2 2 2 3
WOERSTN
1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 EHIHYO 1 1 1 1 1 1 1 1 1 1 1
0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 EKHYO 0 0 0 0 0 0 0 0 0 0 0
10 10 WHST10
9 9 9 9 9 9 9 9 9 1 1
DWFIL WHMOD3 WEYINV WECINV WHRFTH PCMAIN
JSWAP 2 1 WEYDL2 WECDL2 WHRFIV SIQINV 1 WHINV2 EIQINV 0 1 0 MOH WCKINV IENINV WEPCM SHRST11 EHRST11 WCKEON PHREF11 6 6 EPLHS WKHYO RKHYO JFMINT POEINV VSPD1 BVIE5 STREND 4 2 2 2 5 5 EHINV WHINV RHINV 4 4 EVINV WVINV RVINV 3 3 NTPAL WS262 RS262
WHED10 KWST10 KWED10 10 10 10 2 2
RPLHS HYJ3 HIJ3 2 2 VFILOFF RSTDEL 1 1 WVST8 WVED8 VL8 WVMSK7 RVMSK7 7 7 7 7 7 7 KJV7 ATFLD7 STVS7 7
2 2 2 2 2 2 2 2 2 2 2
JVLOINV WKYFRM MAINRST MSKOFF INT3S2 0 4 VSKOFF 3 1 1 1 ATSTRV JVSCRL 3 KSKOFF 2 0 0 0 ATSTRH 1 BHRN3 ATMH3 STMH3 AT2CHG 2 1 RANDM 0 2 2 2
JWRTON FIELD MWBACK MULT BHIE5 BVRN3 ATMV3 STMV3
0 HIE9 KJH9 1 1 1 STHS9
BVWE8 8 8 0 0 0 8
Note2: Set 0 in blank columns.
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TC90A66F
Sub Address Dec 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 FRAON
BMASKON
MSB 15 CHMV3 14 2 13 1 12 0 11 CHMH3 10 2 9 1 RH9 YCMF2 KD15 KD31 YCMF1 14 30 YCMN 13 29 C2HFT 12 28 Y2HFT 11 27 W1NSEL 10 26 THRUY 9 25 8 0 8 KMODE 8 24 7 ATLV3 7 THRUYC 7 23 HFSPAIV VFN3 2 1 0 VFYTH VKOS4 6 2 6 YDL2 6 22 5 1 5 1 5 21 4 0 4 0 4 20 3 ATLH3 3 KTC 3 19 YLPFCH 3 2 2 2 KTB 2 18 THRUC 2 1 1 1 KTA 1 17 CLPFTH 1
LSB 0 0 0 OFSET 0 16 YLPFTH 0
SYCINV
PCMAIN
STHRU
CBYS
ABYS
ACYS
Note2: Set 0 in blank columns.
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TC90A66F
Sub Address Dec 4D 4E 4F 50 51 52 53 54 55 56 57 58 59 5A 5B 5C 5D 5E 5F 60 61 62 63 64 65 66 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102
RMHTES10 RMHCNT11 RHMBLE11 RHMBLS11
MSB 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
LSB 0
10 10
9 9
RVMBLE9 RVMBLS9
8 8 8 8 0
7 7 7 7 MFRAY7
6 6 6 6 6
5 5 5 5 5
4 4 4 4 4
3 3 3 3 3
2 2 2 2 2
1 1 1 1 1
0 0 0 0 0
MFRAIQ7
6
5
4
3
2
1
10
9
RMVCNT9
8 8 8
7 7 7
6 6 6
5 5 5
4 4 4
3 3 3
2 2 2
1 1 1
0 0 0
9
Note2: Set 0 in blank columns.
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TC90A66F
Sub Address Dec 67 68 69 6A 6B 6C 6D 6E 6F 70 71 72 73 74 75 76 77 78 79 7A 7B 7F 103 104 105 RMWSEL 106 YSCMVON 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 127 AUTOIN FHWE3 FHWS3 FVWE3 FVWS3 2 2 2 2 1 1 1 1 0 0 0 0
YSAMVON YSBMVON
MSB 15 14 13 12 11 10 9 8
RMVTES8
LSB 7 7 6 6
RMHMOV6 RMVMOV6
5 5 5 5 2 5 5 5 5
4 4 4 4 1 4 4 4 4
3 3 3 3
RMHSEL4
2 2 2 2 3 2 2 2 2
1 1 1 1 2 1 1 1 1
0 0 0 0 1 0 0 0 0
RHMDN 9 9 RVFRE9 RVFRS9
RMHUP 8 8 8 8
RMVSEL4
3 6 6 6 6
RHFRE11 RHFRS11 FHEON FVEON
10 10 FHSON FVSON
7 7 7 7
3 3 3 3
Note2: Set 0 in blank columns.
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TC90A66F
Outline of I C Bus Control Format
I2C bus control for the TC90A31F conforms to the Philips format.
2
Data Transfer Format
S Slave address 7-bit MSB MSB 0A Sub address 8-bit MSB A XXXXXXXX 8-bit MSB A XXXXXXXX 8-bit AP
S: start condition P: stop condition A: acknowledge (1) Start and stop conditions
SDA
SCL S Start condition when clock line = H, defined at the falling edge of data line. P Stop condition When clock line = H, defined at the rising edge of data line.
(2)
Bit transfer
SDA
SCL
Do not change SDA.
SDA may be changed.
Data are valid only when clock pulse = H (including rising/falling edges).
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TC90A66F
(3) Acknowledge
SDA from master High impedance
SDA from slave
High impedance
SCL from master 1 S 8 9
(4)
A6 0
Slave address
A5 0 A4 1 A3 0 A2 0 A1 1 A0 1 R/W 0
Purchase of TOSHIBA I2C components conveys a license under the Philips I2C Patent Right to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips.
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TC90A66F
I C Bus Functions (write)
Sub Address Hex 1D Dec 29 15 14 10-0 1E 30 15-12 DWFIL JSWAP WHST10-0 WHMOD3-0 Image compression switching PAP (L) image compression (H) Data Signal Name Function
2
Memory write control S/E inversion Horizontal write start position Horizontal reduction ratio 1/16 (0H) 1/8 (1H) 2/5 (6H) 4/5 (CH) 1/2 (7H) 1/5 (2H) 3/5 (8H)
inversion (H) (used at right-and-left picture swapping)
1/4 (3H) 5/8 (9H)
1/3 (4H) 2/3 (AH)
3/8 (5H) 3/4 (BH)
7/8 (CH) 15/16 (EH) 16/16 (FH) inversion (H)
11 10-0 1F 31 15 13-12
WCKINV WHED10-0 WEYINV WEYDL1-0
Memory WCK phase inversion Horizontal write stop position
Memory Y-signal WE polarity inversion Memory Y-signal WE delay adjustment delay 0 (0) delay 1 (1) delay 2 (2)
polarity inversion (H)
delay-1 (3)
11 10-0 20 32 15 14 13-12
IENINV KWST10-0 WECINV WECDL2 WECDL1-0
Memory IE polarity inversion
polarity inversion (H)
Horizontal filter processing start position Memory C-signal WE polarity inversion normal (L) polarity inversion (H)
when 2M memory mode H3/4 (WHMOD3-0 = BH) is set (H)
Memory C-signal WE delay adjustment delay 0 (0) delay 1 (1) delay 2 (2) delay-1 (3)
11 10-0 21 33 15 14 13 12 11-0 22 34 15 14 13 11-0 23 35 12 11-0 24 36 15-8 7-0 25 37 15-8 7-0 26 38 15 14 13 12 11 7 6-0
WEPCM KWED10-0 WHRFTH WHRFIV WHINV2 MOH SHRST11-0 PCMAIN SIQINV EIQINV EHRST11-0 WCKEON PHREF11-0 SCLPST7-0 SCLPED7-0 ECLPST7-0 ECLPED7-0 WPLHS EPLHS EHINV EVINV NTPAL RPLHS HDWDT7-1
Memory WE for 1-picture
1-picture processing (H)
Horizontal filter processing stop position HREF signal through function phase comparison (L) through (H)
Polarity inversion of HREF signal
polarity inversion (H) polarity inversion (H)
Polarity inversion of HD signal for phase comparison Field memory use signal YCS (L) PAP IC (H)
S-system horizontal phase reference 1-picture processing 1-picture processing (H) I/Q inversion (H)
2M memory S system/4M memory-I/Q inversion 2M memory E system-I/Q inversion E-system horizontal phase reference E-system operating control
I/Q inversion (H)
E-system operation (H) NTSC4M/2M [95D]
PLL divider counter cycle for write S-system clamp pulse start position
S-system clamp pulse stop position (start setting value < stop setting value) E-system clamp pulse start position E-system clamp pulse stop position (start setting value < stop setting value) Through function for S-system phase comparison HD signal Through function for E-system phase comparison HD signal E-system HD polarity inversion E-system VD polarity inversion at negative polarity input (L) at negative polarity input (L) through (H) through (H) polarity inversion (H) polarity inversion (H)
NTSC/PAL switching for typical detector circuit
NTSC (L) PAL (H) through (H)
Through function for phase comparison HD signal for read
Pulse width adjustment function for phase comparison HD signal for read (change in units of W1CK)
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Sub Address Hex 27 Dec 39 15 14 13 12 11 10-8 7-3 2 1 0 28 40 15 14 13 12 11 10-8 7-0 29 41 15 14 13 12 11 10 9 8-0 2A 42 15 14 13 9 8-0 2B 43 15 14-13 12 8-0 2C 44 15 14-9 8-0 WHIHYO WKHYO WHINV WVINV WS262 HYJ3-1 WVMSK7-3 WOERSTN EHIHYO EKHYO RHIHYO RKHYO RHINV RVINV RS262 HIJ3-1 RVMSK7-0 JVLOCHG JFMINT JVLOINV WKYFRM MAINRST MSKOFF VFILOFF WVST8-0 JWRTON POEINV INT3S2 RSTDEL WVED8-0 FIELD VSPD1-0 JVSCRL VL8-0 MWBACK BVIE5-0 BVWE8-0 S-system forced non-standard S-system forced standard forced non-standard (H) Data Signal Name Function
forced standard (H) at negative polarity input (L) at negative polarity input (L) polarity inversion (H) polarity inversion (H)
S-system HD signal polarity inversion S-system VD signal polarity inversion S/E-system odd/even inversion
263 (L) 262 (H)
Read S/E-system standard inversion slice level S/E-system VD masking (each 16 lines) Odd/even generator circuit clear stop E-system forced non-standard E-system forced standard forced non-standard (H)
forced standard (H) forced non-standard (H)
Forced non-standard for read Forced standard for read
forced standard (H)
Horizontal direction (HD) signal polarity inversion for read at negative polarity input (L) polarity inversion (H) Vertical direction (VD) signal polarity inversion for read at negative polarity input (L) polarity inversion (H) Odd/even inversion for read 263 (L) 262 (H)
S/E-system non-standard decision inversion slice level for read VD masking for read (each two lines) Change of vertical reduction center Field memory initialize initialize (H) normal (H) center of gravity change (H)
Change of vertical reduction center direction Forced frame write processing
forced frame (H) 1-picture processing (H)
Memory reset switching at 1-picture processing VD masking function off during WE Fixed to L Vertical write start line Write on/off Fixed to L Memory initialize width change Fixed to L Vertical write stop line Only 1-field write 1-field (H) 3V (L) 2V (H) still (L) live (H)
VD mask off (H)
Scroll down speed change Scroll down on/off off (L) on (H) normal [001H]
Number of lines to be moved for vertical reduction center Background on/off off (L) on (H)
[2CH: MWBACK = 1] block vertical interval [2CH: MWBACK = 1] number of block lines
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TC90A66F
Sub Address Hex 2D Dec 45 15 14 13 MULT STREND VSKOFF Multi-search strobe function on/off Fixed to L [2DH: MULT = 1] write block position change function on (L) off (H) on (H) Data Signal Name Function
When set to off, only one picture (upper left) of strobe mode is motion picture. (effective for ATSTRV, H = 1) 12 10 9-0 KSKOFF RANDM HIE9-0 [2DH: MULT = 1] reference skip function off Fixed to L [2DH: MULT = 1] horizontal skip width [2CH: MWBACK = 1] number of block pixels 2E 46 15-10 9-0 2F 47 15-12 11-8 7-0 30 48 15-12 11-8 7-0 31 49 15-12 11-8 7-0 32 50 13 12 11 9-0 33 51 15-12 11-8 7-4 3-0 34 52 9-0 BHIE5-0 KJH9-0 BVRN3-0 BHRN3-0 KJV7-0 ATMV3-0 ATMH3-0 ATFLD7-0 STMV3-0 STMH3-0 STVS7-0 ATSTRV ATSTRH AT2CHG STHS9-0 CHMV3-0 CHMH3-0 ATLV3-0 ATLH3-0 RH9-0 [2CH: MWBACK = 1] block horizontal interval [2DH: KSKOFF = 0] reference skip horizontal position [2CH: MWBACK = 1] number of vertical blocks (setting value: number of vertical blocks - 1) [2CH: MWBACK = 1] number of horizontal blocks (setting value: number of horizontal blocks - 1) [2DH: KSKOFF = 0] reference skip vertical position Number of strobe mode vertical blocks (setting value: number of vertical blocks - 1) Number of strobe mode horizontal blocks (setting value: number of horizontal blocks - 1) [2DH: MULT = 1] write field interval (00H = 2Fi, 01H = 4Fi ) on (L) off (H)
[2DH: MULT = 1] vertical block position for 1 motion picture (specified block - 1) [2DH: MULT = 1] horizontal block position for 1 motion picture (specified block - 1) [2DH: MULT = 1] number of vertical block lines [2DH: MULT = 1] vertical strobe function multi search (L) strobe (H) multi search (L) strobe (H) on (H)
[2DH: MULT = 1] horizontal strobe function
[2DH: MULT = 1] strobe vertical 2-row write function
[2DH: MULT = 1] number of horizontal block pixels (setting value: number of block pixels - 3) [32H: AT2CHG = 1] strobe row 2 [32H: AT2CHG = 1] strobe line 2 [32H: AT2CHG = 1] strobe row 1 [32H: AT2CHG = 1] strobe line 1 [2DH: MULT = 1] number of multi search horizontal pixels (setting value: horizontal pixels - 3) = 15H: field memory horizontal read size In Multi Search, Strobe mode Number of pixels = (number of block pixels) x (number of horizontal blocks)
35
53
15 14 13 12 11 10 9 8 7 6-4 3-1 0
YCMF2 YCMF1 YCMN C2HFT Y2HFT W1NSEL THRUY KMODE THRUYC YDL2-0 KTC-A OFSET
YCMIX signal (M/N type) polarity inversion
polarity inversion (H) polarity inversion (H)
YCMIX signal (before multiplier) polarity inversion Compression switching M/N compression (L)
1/N compression (H) on (H) on (H)
Color signal (I/Q) binary interpolation circuit on/off Luminance signal binary interpolation circuit on/off Reduction processor circuit switching Through output on/off for Y-signal only
M/N (L) 1/N (H) on (H) 1/N processing (L) on (H) M/N processing (H)
Horizontal filter coefficient mode switching
[35H: YCMN = 1] horizontal filter through on/off Y signal delay adjustment Number of filter coefficients Fixed to L
0Hex = 1, 1Hex = 2,
7Hex = 8
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TC90A66F
Sub Address Hex 36 37 38 Dec 54 55 56 15-0 15-0 7 3 2 1 0 39 57 11-8 KD15-0 KD31-16 HFSPAIV YLPFCH THRUC CLPFTH YLPFTH VFN3-0 Horizontal filter coefficient 1 (KD 3-0)~coefficient 8 (KD31-28) 1/N compression: 10H-setting value (complement) M/N compression: Hex Data Signal Name Function
[4M mode] polarity inversion of Y/C separation control signal before HFIL stage polarity inversion (H) LPF for Y signal switching Stage 2 (L) stage 1 (H) on (H)
C-signal-only through output on/off LPF for C signal on/off LPF for Y signal on/off on (H) on (H)
Vertical compression ratio (setting value: denominator - 1) (1/2 1, 1/3 2, 1/4 3, 3/4 3, 1/5 -4, 1/6 5, 1/8 7) Select from the above reduction ratios.
5 4-0
VFYTH VKOS4-0
Vertical filter through on/off
on (H)
RAM address specification for vertical filter coefficient Set according to the specified vertical reduction ratio as follows: 1/3 (00H), 1/4 (03H), 1/2 (07H), 3/4 (09H), 5/6 (0DH), 1/8 (13H), 1/5 (1BH)
3B
59
11 10 8
SYCINV PCMAIN STHRU AUTOIN
Polarity inversion of Y/C separation control signal 1-picture processing 1-picture processing (H) on (H)
polarity inversion (H)
SEL block through on/off
7F
127
8
Vertical filter SRAM data transmission Set to L for no vertical reduction.
Auto Increment mode [H]
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TC90A66F
I C Bus Functions (read)
Sub Address Hex 00 Dec 00 15-13 12 11 10 9-8 7 6 01 01 13 12 11 10 9 02 02 15-12 11-8 7-0 03 03 15-12 11-8 7-0 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 09 10 11 12 13 14 15 16 17 18 19 20 21 22 23 11-0 11-0 9-0 9-0 11-0 11-0 9-0 9-0 11-0 11-0 9-0 9-0 11-0 9-0 14 13 12 11-0 18 24 15 14 13 12 9-0 MYPH2-0 MIQPH0 RRSTINV RCKINV RREPH1-0 M4M2 SESW YSBACT FRACLR YSCCLR YSBCLR YSACLR MBLKIQ7-4 MBLKIQ3-0 MBLKY3-0 MMWIQ7-0 MMWIQ3-0 MMWY7-0 Y signal phase adjustment for read I/Q signal phase adjustment for read Polarity inversion of field memory read reset (RRST) signal Polarity inversion of field memory read clock (PCK) signal inversion (H) inversion (H) inversion (H) Data Signal Name Function
2
Phase adjustment of field memory read enable (RRE) signal 4M memory/2M memory mode switching S/E system control switching YS off (L) on (H) off (L) on (H) off (L) on (H) off (L) on (H) off (L) on (H) 4M (L) 2M (H)
S system (L) E system (H)
Frame signal YS (E system) YS (external) YS (S system)
Blanking level (I) Blanking level (Q) Blanking level (Y) Background level (I) Background level (Q) Background level (Y)
PHYSAE11-0 YS horizontal stop position (S system) PHYSAS11-0 YS horizontal start position (S system) RVYSAE9-0 RVYSAS9-0 YS vertical stop position (S system) YS vertical start position (S system)
RHYSBE11-0 YS horizontal stop position (external) RHYSBS11-0 YS horizontal start position (external) RVYSBE9-0 RVYSBS9-0 YS vertical stop position (external) YS vertical start position (external)
RHYSCE11-0 YS horizontal stop position (E system) RHYSCS11-0 YS horizontal start position (E system) RVYSCE9-0 RVYSCS9-0 RHSIZ11-0 RVSIZ9-0 ROEFON RGAME DWSW RRH11-0 FRFI ROEALT RFISW RFALT RRV9-0 YS vertical stop position (E system) YS vertical start position (E system) Field memory horizontal read size (set number of horizontal pixels - 3) Field memory read size (vertical) Field memory read/write phase control for write Game mode display on (H) PIP (H) on (H)
PIP display (vertical 1/2 size or smaller)
Field memory horizontal read start position Field/frame display switching Odd/even switching Field/frame display switching (field memory read/write phase control on/off) frame (H) field (L) Field memory read/write phase control at memory read Field memory vertical read start position normal (H) frame (L) field (H)
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TC90A66F
Sub Address Hex 19 1A Dec 25 26 9-0 9-0 RWRN9-0 RWRA9-0 Field memory read/write phase control start (at standard) Field memory read/write phase control start (at non-standard) 19H and 1AH are control registers at frame display (PIP, DW). 19H is for when main/sub picture is standard signal; 1AH is for when either main/sub picture is non-standard signal. How to calculate the setting value: Sub address 15H: field memory horizontal read size = A Sub address 16H: field memory vertical read size = B (A + 3) x B - 600 256 Data Signal Name Function
(calculate in decimal)
Input the result of the above calculation in hexadecimal (19H and 1AH have the same value). 1B 27 15 14 13 12 11-0 1C 40 28 64 11-0 6 5 RHRFTH RHRFIV RHINV2 RCKCHG PRHP11-0 Control output mode for RHREF signal output control Polarity inversion of RHREF signal forced output (H)
polarity inversion (H) polarity inversion (H)
HD polarity inversion of RHREF signal output control Read clock switching normal (L)
Read horizontal reference (PLL counter decoded value)
RPLLPH11-0 PLL counter for read (fH setting) FRAON BWASKON Frame signal off (L) on (H) background (L) image (H)
Background/image switching
(Set background to YIQ level at 03H.) 2 1 0 5D 5E 5F 60 61 93 94 95 96 97 11-0 11-0 9-0 9-0 15-12 11-8 7-0 64 65 66 67 68 69 100 101 102 103 104 105 11-0 9-0 10-0 8-0 6-0 15 6-0 CBYS ABYS ACYS YSB > YSC (L) YSB < YSC (H) (YSA: S system, YSB: external, YSC: E system) YSA > YSB (L) YSA < YSB (H) YSA > YSC (L) YSA < YSC (H)
RHMBLE11-0 Blanking horizontal stop position RHMBLS11-0 Blanking horizontal start position RVMBLE9-0 RVMBLS9-0 MFRAIQ7-4 MFRAIQ3-0 MFRAY7-0 Blanking vertical stop position Blanking vertical start position Frame level (I) Frame level (Q) Frame level (Y)
RMHCNT11-0 Wipe signal horizontal reference (center) RMVCNT9-0 Wipe signal vertical reference (center)
RMHTES10-0 Wipe signal horizontal phase range (width) RMVTES8-0 Wipe signal vertical phase range (width)
RMHMOV6-0 Wipe signal horizontal operating speed RMWSEL Wipe signal system select window (L) cross (H)
RMVMOV6-0 Wipe signal vertical operating speed
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TC90A66F
Sub Address Hex 6A Dec 106 15 11 10 9 8 7 6 5 4 3 2 3-2 1-0 6B 107 15-12 11-0 6C 108 15-12 11-0 6D 109 15-12 11 10 9-0 6E 110 15-12 11 10 9-0 YSCMVON YSAMVON YSBMVON RMHDN RMHUP RMVSEL4 RMVSEL3 RMVSEL2 RMVSEL1 RMHSEL4 RMHSEL3 RMHSEL2 RMHSEL1 FHWE3-0 RHFRE11-0 FHWS3-0 RHFRS11-0 FVWE3-0 FHEON FHSON RVFRE9-0 FVWS3-0 FVEON FVSON RVFRS9-0 E-system wipe S-system wipe External wipe Wipe counter off (L) on (H) off (L) on (H) off (L) on (H) up (L) down (H) reset (L) off (L) on (H) off (L) on (H) Data Signal Name Function
Wipe counter reset Vertical wipe (top) Vertical wipe Fixed to H Fixed to L
(bottom)
Horizontal wipe (right) Horizontal wipe (left) Fixed to H Fixed to L
off (L) on (H) off (L) on (H)
Frame horizontal width (stop position) Frame horizontal stop position Frame horizontal width (start position) Frame horizontal start position Frame vertical width (stop position) Frame horizontal (stop position) Frame horizontal (start position) Frame vertical stop position Frame vertical width (start position) Frame vertical (stop position) Frame vertical (start position) Frame vertical start position off (L) on (H) off (L) on (H) off (L) on (H) off (L) on (H)
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TC90A66F
Description of I C Bus Data for Read
1. Frame Display
(1) (2) (3) Y signal can be set with 8-bit precision; I/Q signal with 4-bit precision. Frame width can be set in 4 bits (16 types). Set frame details using the following registers: RHFRS: frame horizontal start position RHFRE: frame horizontal stop position FHWS: frame horizontal width (start position) FHWE: frame horizontal width (stop position) RVFRS: frame vertical start position RVFRE: frame vertical stop position FVWS: frame vertical width (start position) FVWE: frame vertical width (stop position)
2
FVWS RVFRS
Sub picture
FHWS
FHWE
RVFRE PHFRS FVWE RHFRE
2. YS and Blanking Setting
(1) (2) Set the YS signal timing using the following registers. Set horizontal start and stop positions, and vertical start and stop positions for blanking.
PHYSAS PHYSAE
blanking RVYSAS RVYSCS
Sub picture (S)
Sub picture (E)
RVYSAE blanking
RVYSCE
RHYSCS
RHYSCE
YS horizontal start position (S system) YS horizontal stop position (S system) YS horizontal start position (E system) YS horizontal stop position (E system) YS vertical start position (S system) YS vertical stop position (S system)
YS vertical start position (E system) YS vertical stop position (E system) Blanking horizontal start position Blanking horizontal stop position Blanking vertical start position Blanking vertical stop position
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TC90A66F
Settings of Special Effect Functions
3. Scroll Down
Special effect function used when selecting 2-picture, 1-picure, or PIP display. The function freezes the image signal before selection then moves the image after selection from the top. (1) 1-field display 18h (24) FRFI = H (field display) FRISW = L (field display) (2) Write stop 2Ah (42) JWRTON = L (Write stop) (3) Select channel change start Change channel after write actually stopped. (4) Scroll down function environment setting 29h (41) MAINRST =H =H WKYFRM 2Bh (43) FIELD =H (5) Scroll down start 2Bh (43) JVSCRL =H (6) Write start 2Ah (42) JWRTON =H (7) Scroll down standby time (do not change frame processing during standby) NTSC PAL 2BH: VSPD Number of write lines (240 valid lines) (282 valid lines) Setting value LL 2 120Fr (4.0 s) 141Fr (5.6 s) LH 4 60Fr (2.0 s) 70Fr (2.8 s) HL 6 40Fr (1.3 s) 47Fr (1.9 s) HH 7 34Fr (1.1 s) 40Fr (1.6 s) (8) Write processing change (frame processing) 29h(41) WKYFRM =L (after 1 field) 29h(41) MAINRST =L 2Bh(43) FIELD =L JVSCRL =L (9) Read processing change (frame processing) After sending write processing data, count four fields of VD for read, then send the following data. (After new image signal is written to memory, frame is displayed.) 18h (24) FRFI =L =H FRISW
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TC90A66F
Settings of Special Effect Functions
4. Wipe Function
(1) Wipe on/off 6Ah (106) YSCMVON E system wipe on (H)/off (L) YSAMVON S system wipe on (H)/off (L) YSBMVON External wipe on (H)/off (L) Wipe signal center and width settings (horizontal and vertical) 64h (100) RMHCNT Wipe signal horizontal reference (center) 65h (101) RMVCNT Wipe signal vertical reference (center) 66h (102) RMHTES Wipe signal horizontal phase adjustment (width) 67h (103) RMVTES Wipe signal vertical phase adjustment (width) Wipe signal speed settings (count number of vertical sync signal) 68h (104) RMHMOV Wipe signal horizontal operating speed large slow 69h (105) RMVMOV Wipe signal vertical operating speed large slow Wipe direction setting 6Ah (106) RMVSEL4 Up on (H)/off (L) RMVSEL3 Down on (H)/off (L) RMHSEL4 Right on (H)/off (L) RMHSEL3 Left on (H)/off (L) Wipe type setting 69h (105) RMWSEL window (L) cross (H)
(2)
(3)
small fast small fast
(4)
(5)
window
cross
(6)
Wipe operating control 6Ah (106) RMHDH Wipe counter UP (L)/DOWN (H) RMHUP Wipe counter reset reset (L) (1) Start from wipe close RMHDN = L, RMHUP = L (wipe close: initial state) RMHDN = L, RMHUP = H RMHDN = H, RMHUP = H (wipe open) (2) Start from wipe open RMHDN = H, RMHUP = L (wipe open: initial state) RMHDN = H, RMHUP = H RMHDN = L, RMHUP = H (wipe close) *: Send in order of to .
*: When the center is changed, make initial settings.
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Maximum Ratings (VSS = 0 V, Ta = 25C)
Characteristics Power supply voltage Symbol VSS, VDD VIN1 Input voltage VIN2 PD (Note4) Storage temperature Tstg -55 to 125 C Rating VSS to VSS + 4.0 -0.3 to VDD + 0.3 -0.3 to 525 (Note3) 2000 mW V Unit V
Power dissipation
Note3: Applicable to WVDE, WHDE, WCKE, WVDS, WHDS, WCKS, RDAC0 to RDAC7, RDAY0 to RDAY7, RCK, RHD, RVD, SCL, and SDA pins. Note4: When using the IC at Ta = 25C or higher, reduce 20.0 mW per degree.
Power Dissipation Reduction Against Higher Temperature (when mounted on board)
2000
Power dissipation (mW)
1500 500
1100
500
0
25
50
70
100
125
Operating temperature (C)
Recommended Operating Conditions (VSS = 0 V)
Characteristics Power supply voltage Input voltage Operating temperature Symbol VDD VIN Topr Test Condition Min 3.0 0 -20 Typ. 3.3 Max 3.6 VDD 70 Unit V V C
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Electrical Characteristics
1. DC Characteristics Operating Conditions: VDD = 3.0 to 3.6 V, VIN = 0 to VDD, Ta = -20 to 70C, VSS = 0
Characteristics Power dissipation Symbol IDD Test Circuit Test Condition NTSC Min VDD x 0.8 VIH Schmitt trigger input CMOS input Low-level input voltage VIL VDD x 0.8 VDD x 0.8 IIH IIL VOH1 VOH2 Low level Schmitt trigger hysteresis voltage VOL1 VOL2 VH VIN = VDD VIN = VSS IOH1 = -4 mA IOH2 = -8 mA IOL1 = 4 mA IOL2 = 8 mA -10 -10 2.4 2.4 Typ. 0.5 0.4 0.4 V V (Note7) (Note8) (Note6) Max 250 VDD 5.25 5.25 VDD x 0.2 VDD x 0.2 VDD x 0.2 10 10 A V V Unit mA (Note5) (Note9) (Note6) (Note5) (Note9) (Note6) (Note5) (Note6) (Note7) (Note8) Terminal
CMOS input High-level input voltage
Schmitt trigger input
High level Input current Low level High level Output voltage
Note5: TIN9-0, RMCKI, PWRST, TIMRST, IICNR, SADSEL, TST4-0, WHREFE, WHREFS, EWIEN, EWEN, EWRST, WIEN, WEN, WRST, WDAC7-0, WDAY7-0, REN, RRST, EREN, ERRST, RHREF, T107-100, EWMCK, WMCK, RMCK Note6: WVDE, WHDE, WVDS, WHDS, RHD, RVD, SCL, SDA Note7: WHREFE, WHREFS, EWIEN, EWEN, EWRST, WIEN, WEN, WRST, WDAC7-0, WDAY7-0, REN, RRST, EREN, ERRST, RHREF, SDA, T107-100, EWMCK, WMCK, RMCK Note8: EWMCK, WMCK, RMCK Note9: WCKE, WCKS, RDAC0-7, RDAY0-7, RCK
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2. AC Characteristics Operating Conditions: VDD = 3.3 to 3.6 V, VIN = 0 to VDD, Ta = -20 to 70C, VSS = 0
Characteristics Operating frequency condition TSUP1 Input setup time TSUP2 THLD1 Input hold time THLD2 Tpd1 Tpd2 Tpd3 Tpd4 Tpd5 Tpd6 Tpd7 Tpd8 Tpd9 Tpd10 Output transfer delay time Tpd11 Tpd12 Tpd13 Tpd14 Tpd15 Tpd16 Tpd17 Tpd18 Tpd19 Tpd20 CL = 10.8 pF Vth = 2 V WCK = 37.8 MHz RCK = 37.8 MHz Symbol Test Circuit Test Condition NTSC mode Operating frequency: 20 MHz Operating frequency: 20 MHz 5 5 3 5 5 4 6 6 6 6 6 6 7 6 6 6 6 6 4 4 6 5 6 6 Min Typ. 20 Max 20 16 22 18 21 17 21 17 24 22 ns 22 19 22 19 18 15 20 17 20 17 Unit MHz ns Remarks
ns
3. 1 ADC Characteristics Operating Conditions: VDD = 3.3 V, Ta = -20 to 70C, VSS = 0
Characteristics Non-linear error Symbol ILE Test Circuit Test Condition VDD = 3.3 V DACK = 10 MHz VDD = 3.3 V DACK = 10 MHz VDD = 3.3 V DACK = 10 MHz VDD = 3.3 V DACK = 10 MHz Min -3 Typ. Max +3 Unit LSB
Differential non-linear error
DLE
-2
+2
LSB
FULL SCA Analog input voltage ZERO SCA
VIFS
2.2
V
VIZS
1.1
V
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3. 2 Clamp and Multiplexer Operating Conditions: VDD = 3.3 V, Ta = -20 to 70C, VSS = 0
Characteristics Clamp Y Clamp C Multiplexer Symbol Test Circuit Test Condition Min Typ. 63 136 5 Max Unit LSB LSB MHz
4. DAC Characteristics Operating Conditions: VDD = 3.3 V, Ta = -20 to 70C, VSS = 0
Characteristics Non-linear error Symbol ILE Test Circuit Test Condition VDD = 3.3 V DACK = 20 MHz VDD = 3.3 V DACK = 20 MHz VDD = 3.3 V DACK = 20 MHz VDD = 3.3 V DACK = 20 MHz Min -3 Typ. Max +3 Unit LSB
Differential non-linear error
DLE
-2
+2
LSB
FULL SCA Analog input voltage ZERO SCA
VIFS
VDD
V
VIZS
VREF
V
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TC90A66F
AC Characteristic Timing Charts
Write
WCK Tpd1 WMCK Tpd3 WRST Tpd5 WENY Tpd7 WENC Tpd9 WIE Tpd11 WDAY 7 to 0 Tpd13 WDAC 7 to 0 Tpd14 Tpd12 Tpd10 Tpd8 Tpd6 Tpd4 Tpd2
Read
RCK Tpd15 RMCK Tpd17 RRST Tpd19 REN Tpd20 Tpd18 Tpd16
THLD1 RMCKI TSUP1
THLD2 RDAY 7 to 0 TSUP2 RDAC 7 to 0
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Application Circuit
3.3 V GND
YOUT IOUT QOUT 0.1 F 2.2 k 0.1 F 5.1 k 0.1 F 0.1 F 10 F 1 k SDA SCL YS RHD RVD
10 F
10 F
2.7 k
TEST0
TEST1
TEST2
TEST3
TEST4
T100
T101
T102
T103
T104
T106
CNT3
CNT4
CNT6
CNT5
T107
VB1
VB2
T105
SCL
SADSEL
DAVSS
VSS
ADBIAS
VREF
DAVDD
DAVDD
SDA
VDD
VSS
SACN
IICNR
QOUT
YOUT
TESO
IOUT
10 F
144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 21 120 119 118 117 116 115 114 113 112 111 110 109
27 k
321 TIMRST 108 PWRST 107 HYOJUN 106 KAYS 105 YS 104 RVD 103 RHD 102 VDD 101 RCK 100 RHREF 99 VSS 98 RMCKI 97 RMCK 96 ERRST 95 EREN 94 RRST 93 REN 92 RDAY7 91 RDAY6 90 RDAY5 89 RDAY4 88 RDAY3 87 RDAY2 86 RDAY1 85 RDAY0 84 VDD 83 RDAC7 82 RDAC6 81 RDAC5 80 RDAC4 79 RDAC3 78 RDAC2 77 RDAC1 76 RDAC0 75 WDAY0 74 WDAY1 73 28 26 24 22 20 18 16 14 12 10 8 6 4 2 MSM51V8221 10 F (Y/S) 27 25 23 21 19 17 15 13 11 9 7 5 3 1 10 F 10 F TP1 TP2 TP3 4 3.3 pF 5 100 F 0.1 F 1 2 3 4 5 6 7 TLC2933 14 13 12 11 10 9 8 2 k 0.1 F 3 k 560 100 F 0.1 F 10 F TC7508F (Inverter)
10 F YINS IINS QINS 0.1 F 0.1 F 10 F 0.1 F 0.1 F 0.1 F 0.1 F 0.1 F 10 F YINE IINE QINE 0.1 F 0.1 F 10 F 0.1 F 10 F
1 ADVDD 2 YINS 3 ADVSS 4 IINS 5 ADVDD 6 QINS 7 ADVSS 8 VRTY 9 VRBY 10 VRTC 11 VRBC 12 ADVDD 13 YINE 14 ADVSS 15 IINE 16 AVDD 17 QINE 18 AVSS 19 VDD 20 CNT2 21 CNT1 22 CNT0 TC90A66F
TP
23 CLAMP 24 TIN9 25 TIN8 26 TIN7 27 TIN6 28 TIN5 29 TIN4 30 TIN3 31 TIN2 32 TIN1 33 TIN0
WVDE WHDE WVDS WHDS
34 WVDE 35 WHDE WHREFE WHREFS 36 VSS WCKE EWMCK WDAC7 WDAC6 WDAC5 WDAC4 WDAC3 WDAC2 WDAC1 WDAC0 EWRST WDAY7 WDAY6 WDAY5 WDAY4 WDAY3 WDAY2 EWIEN WMCK
WHDS
WVDS
WCKS
EWEN
HRST
VDD
MOH
VSS
VSS
WRST
WIEN
WEN
VDD
VSS
37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 10 F 10 F
TC7508F (AND)
3.3 pF
1 2 27 k 3
5 4 0.1 F
3.3 pF
4 5
TC7508F (AND)
3 2 1 0.1 F 27 k (C/E) 2 4 6 8 10 12 14 16 18 20 22 24 26 28 MSM51V8221 100 F 1 3 5 7 9 11 13 15 17 19 21 23 25 27
7654321 TLC2933 8 9 10 11 12 13 14 100 F 3 k 2 k 560 0.1 F 10 F (E)
100 F
7654321 TLC2933 8 9 10 11 12 13 14 2 k 0.1 F 560 0.1 F 10 F 100 F 3 k (S) 10 F
0.1 F
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TC90A66F
Package Dimensions
Weight: 4.64 g (typ.)
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RESTRICTIONS ON PRODUCT USE
000707EBA
* TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the "Handling Guide for Semiconductor Devices," or "TOSHIBA Semiconductor Reliability Handbook" etc.. * The TOSHIBA products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These TOSHIBA products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or bodily injury ("Unintended Usage"). Unintended Usage include atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices, etc.. Unintended Usage of TOSHIBA products listed in this document shall be made at the customer's own risk. * The products described in this document are subject to the foreign exchange and foreign trade laws. * The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA CORPORATION for any infringements of intellectual property or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any intellectual property or other rights of TOSHIBA CORPORATION or others. * The information contained herein is subject to change without notice.
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2001-06-07

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